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Support region padding for MPU programming (requires #127) #146

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e624ec6
Split out SMP tests into their own folder.
thejpster Feb 16, 2026
e50781a
Add GIC SGI SMP example.
thejpster Feb 16, 2026
feddd77
Allocate stacks for all cores
thejpster Feb 21, 2026
740a71d
Adjust comment text to avoid markdown warning
thejpster Mar 6, 2026
374029a
Make it easier to set up the MPU
thejpster Mar 6, 2026
3b92c3d
Resolve some clippy lints
thejpster Mar 6, 2026
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56 changes: 0 additions & 56 deletions .cargo/config.toml
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Original file line number Diff line number Diff line change
@@ -1,56 +0,0 @@
[target.armv8r-none-eabihf]
# Note, this requires QEMU 9 or higher
runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -audio none -kernel"

[target.thumbv8r-none-eabihf]
# Note, this requires QEMU 9 or higher
runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -audio none -kernel"

[target.armv7r-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu cortex-r5f -semihosting -nographic -audio none -kernel"

[target.thumbv7r-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu cortex-r5f -semihosting -nographic -audio none -kernel"

[target.armv7r-none-eabi]
# change '-mcpu=cortex-r5' to '-mcpu=cortex-r5f' if you use eabi-fpu feature, otherwise
# qemu-system-arm will lock up
runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nographic -audio none -kernel"

[target.thumbv7r-none-eabi]
# change '-mcpu=cortex-r5' to '-mcpu=cortex-r5f' if you use eabi-fpu feature, otherwise
# qemu-system-arm will lock up
runner = "qemu-system-arm -machine versatileab -cpu cortex-r5 -semihosting -nographic -audio none -kernel"

[target.armv7a-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"

[target.thumbv7a-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"

[target.armv7a-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"

[target.thumbv7a-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu cortex-a8 -semihosting -nographic -audio none -kernel"

[target.armv6-none-eabihf]
runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"

[target.armv6-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"

[target.thumbv6-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm1176 -semihosting -nographic -audio none -kernel"

[target.armv5te-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"

[target.thumbv5te-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"

[target.armv4t-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"

[target.thumbv4t-none-eabi]
runner = "qemu-system-arm -machine versatileab -cpu arm926 -semihosting -nographic -audio none -kernel"
2 changes: 2 additions & 0 deletions .gitignore
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@@ -1,6 +1,8 @@
target
examples/mps3-an536/target
examples/mps3-an536/target-d32
examples/mps3-an536-smp/target
examples/mps3-an536-smp/target-d32
examples/versatileab/target
examples/versatileab/target-d32
Cargo.lock
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4 changes: 3 additions & 1 deletion .vscode/settings.json
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,9 @@
"rust-analyzer.checkOnSave": true,
"rust-analyzer.linkedProjects": [
"./Cargo.toml",
"./arm-targets/Cargo.toml",
"examples/versatileab/Cargo.toml",
"examples/mps3-an536/Cargo.toml"
"examples/mps3-an536/Cargo.toml",
"examples/mps3-an536-smp/Cargo.toml",
]
}
1 change: 1 addition & 0 deletions Cargo.toml
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Expand Up @@ -3,6 +3,7 @@ exclude = [
"arm-targets",
"examples/versatileab",
"examples/mps3-an536",
"examples/mps3-an536-smp",
]
members = [
"aarch32-cpu",
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10 changes: 5 additions & 5 deletions aarch32-cpu/src/pmsav8.rs
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Expand Up @@ -23,7 +23,7 @@ pub enum Error {
/// Found an invalid MAIR selector (only 0..=7 is valid)
InvalidMair(u8),
/// Found a region with invalid alignment
UnalignedRegion(core::ops::RangeInclusive<*mut u8>),
UnalignedRegion(core::ops::RangeInclusive<*const u8>),
}

/// Represents our PMSAv8-32 EL1 MPU
Expand Down Expand Up @@ -224,8 +224,8 @@ impl El2Mpu {
register::Hprselr::write(register::Hprselr(idx as u32));
let hprbar = register::Hprbar::read();
let hprlar = register::Hprlar::read();
let start_addr = (hprbar.base().value() << 6) as *mut u8;
let end_addr = ((hprlar.limit().value() << 6) | 0x3F) as *mut u8;
let start_addr = (hprbar.base().value() << 6) as *const u8;
let end_addr = ((hprlar.limit().value() << 6) | 0x3F) as *const u8;
Some(El2Region {
range: start_addr..=end_addr,
shareability: hprbar.shareability(),
Expand Down Expand Up @@ -385,7 +385,7 @@ pub struct El1Region {
///
/// * The first address must be a multiple of 32.
/// * The length must be a multiple of 32.
pub range: core::ops::RangeInclusive<*mut u8>,
pub range: core::ops::RangeInclusive<*const u8>,
/// Shareability of the region
pub shareability: El1Shareability,
/// Access for the region
Expand Down Expand Up @@ -430,7 +430,7 @@ pub struct El2Region {
///
/// * The first address must be a multiple of 32.
/// * The length must be a multiple of 32.
pub range: core::ops::RangeInclusive<*mut u8>,
pub range: core::ops::RangeInclusive<*const u8>,
/// Shareability of the region
pub shareability: El2Shareability,
/// Access for the region
Expand Down
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