LLVM 19.1.0: Fixes

llvm/lib/CodeGen/GlobalISel/PatternGen.cpp

@@ -1,3 +1,3 @@
 //===- llvm/CodeGen/GlobalISel/PatternGen.cpp - PatternGen ---==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
@@ -78,7 +78,7 @@
 #endif
 
 std::ostream *PatternGenArgs::OutStream = nullptr;
 std::vector<CDSLInstr> const *PatternGenArgs::Instrs = nullptr;
 PGArgsStruct PatternGenArgs::Args;
 
 struct PatternArg {
@@ -156,10 +156,10 @@
   operator bool() const { return Type != 0; }
 };
 
 std::string Errors[] = {"success",        "multiple blocks", "expected return",
                         "expected store", "load format",     "immediate format",
                         "format",         "multiple stores"};
 llvm::Statistic *ErrorStats[] = {nullptr,
                                  &PatternGenNumErrorMultipleBlocks,
                                  &PatternGenNumErrorFormatReturn,
                                  &PatternGenNumErrorFormatStore,
@@ -182,7 +182,7 @@
     {CmpInst::Predicate::ICMP_UGE, "SETUGE"},
 };
 
 std::string lltToString(LLT Llt) {
   if (Llt.isFixedVector())
     return "v" + std::to_string(Llt.getElementCount().getFixedValue()) +
            lltToString(Llt.getElementType());
@@ -194,7 +194,7 @@
   return "invalid";
 }
 
 std::string lltToRegTypeStr(LLT Type) {
   if (Type.isValid()) {
     if (Type.isFixedVector() && Type.getElementType().isScalar() &&
         Type.getSizeInBits() == 32) {
@@ -210,8 +210,10 @@
   return "invalid";
 }
 
-std::string makeImmTypeStr(int Size, bool Signed) {
-  return (Signed ? "simm" : "uimm") + std::to_string(Size);
+std::string makeImmTypeStr(int Size, bool Signed, std::string llvm_type) {
+  if (llvm_type.empty())
+    return (Signed ? "simm" : "uimm") + std::to_string(Size);
+  return llvm_type;
 }
 
 struct PatternNode {
@@ -579,15 +581,15 @@
     std::string TypeStr = lltToString(Type);
 
     // ignore bitcast ops for now
-    if (Op == TargetOpcode::G_BITCAST)
+    if ((Op == TargetOpcode::G_BITCAST) || (Op == TargetOpcode::G_CONSTANT_FOLD_BARRIER))
       return Operand->patternString();
 
     return "(" + TypeStr + " (" + std::string(UnopStr.at(Op)) + " " +
            Operand->patternString() + "))";
   }
 
   LLT getRegisterTy(int OperandId) const override {
-    if (OperandId == -1 && Op != TargetOpcode::G_BITCAST)
+    if (OperandId == -1 && Op != TargetOpcode::G_BITCAST && Op != TargetOpcode::G_CONSTANT_FOLD_BARRIER)
       return Type;
     return Operand->getRegisterTy(OperandId);
   }
@@ -623,22 +625,27 @@
   StringRef Name;
   int Size;
   bool Sext;
+  std::string llvm_type;
 
   size_t RegIdx;
 
   RegisterNode(LLT Type, StringRef Name, size_t RegIdx, bool IsImm, int Size,
-               bool Sext)
+               bool Sext, std::string llvm_type)
       : PatternNode(PN_Register, Type, IsImm), Name(Name), Size(Size),
-        Sext(Sext), RegIdx(RegIdx) {}
+        Sext(Sext), llvm_type(llvm_type), RegIdx(RegIdx) {}
 
   std::string patternString() override {
     std::string TypeStr = lltToString(Type);
     bool PrintType = Type.isPointer();
 
     if (IsImm) {
       // Immediate Operands
-      return ("(" + RegT + " ") + (Sext ? "simm" : "uimm") +
-             std::to_string(Size) + ":$" + std::string(Name) + ")";
+      std::string pre;
+      if (llvm_type.empty())
+        pre = (Sext ? "simm" : "uimm") + std::to_string(Size);
+      else
+        pre = llvm_type;
+      return ("(" + RegT + " ") + pre + ":$" + std::string(Name) + ")";
     }
 
     // Vector Types (currently rv32 only)
@@ -937,8 +944,28 @@
     ReadOffset = Offset->getOperand(1).getCImm()->getLimitedValue();
   }
   if (AddrI->getOpcode() == TargetOpcode::G_SELECT) {
-    // TODO: implement this!
-    return pError(FORMAT_LOAD, AddrI);
+    assert(AddrI->getOperand(1).isReg() && "expected register");
+    auto CondInstr  = AddrI->getOperand(1);
+    auto CondReg  = CondInstr.getReg();
+    auto [ErrCond, CondNode] = traverse(MRI, *MRI.getVRegDef(CondReg));
+    if (ErrCond)
+      return PError(ErrCond);
+    assert(AddrI->getOperand(2).isReg() && "expected register");
+    auto TrueInstr  = AddrI->getOperand(2);
+    auto TrueReg  = TrueInstr.getReg();
+    auto [ErrTrue, TrueNode] = traverseRegLoad(MRI, Cur, ReadSize, MRI.getVRegDef(TrueReg));
+    if (ErrTrue)
+      return PError(ErrTrue);
+    assert(AddrI->getOperand(3).isReg() && "expected register");
+    auto FalseInstr  = AddrI->getOperand(3);
+    auto FalseReg  = FalseInstr.getReg();
+    auto [ErrFalse, FalseNode] = traverseRegLoad(MRI, Cur, ReadSize, MRI.getVRegDef(FalseReg));
+    if (ErrFalse)
+      return PError(ErrFalse);
+    auto Node = std::make_unique<TernopNode>(
+        MRI.getType(Cur.getOperand(0).getReg()), AddrI->getOpcode(),
+        std::move(CondNode), std::move(TrueNode), std::move(FalseNode));
+    return PPattern(std::move(Node));
   }
   if (AddrI->getOpcode() != TargetOpcode::COPY)
     return pError(FORMAT_LOAD, AddrI);
@@ -959,7 +986,7 @@
 
   assert(Cur.getOperand(0).isReg() && "expected register");
   std::unique_ptr<PatternNode> Node = std::make_unique<RegisterNode>(
-      Type, Field->ident, Idx, false, Type.getSizeInBits(), false);
+      Type, Field->ident, Idx, false, Type.getSizeInBits(), false, Field->llvm_type);
 
   bool SizeMismatch = (int)Type.getSizeInBits() != ReadSize;
 
@@ -1040,6 +1067,7 @@
 
     return std::make_pair(SUCCESS, std::move(Node));
   }
+  case TargetOpcode::G_CONSTANT_FOLD_BARRIER:
   case TargetOpcode::G_ANYEXT:
   case TargetOpcode::G_SEXT:
   case TargetOpcode::G_ZEXT:
@@ -1141,7 +1169,7 @@
       PatternArgs[Idx].In = true;
       PatternArgs[Idx].Llt = LLT();
       PatternArgs[Idx].ArgTypeStr =
-          makeImmTypeStr(Field->len, Field->type & CDSLInstr::SIGNED);
+          makeImmTypeStr(Field->len, Field->type & CDSLInstr::SIGNED, Field->llvm_type);
 
       if (Field == nullptr)
         return std::make_pair(FORMAT_IMM, nullptr);
@@ -1150,7 +1178,7 @@
       return std::make_pair(
           SUCCESS, std::make_unique<RegisterNode>(
                        MRI.getType(Cur.getOperand(0).getReg()), Field->ident,
-                       Idx, true, Field->len, Field->type & CDSLInstr::SIGNED));
+                       Idx, true, Field->len, Field->type & CDSLInstr::SIGNED, Field->llvm_type));
     }
 
     // Else COPY is just a pass-through.
@@ -1331,6 +1359,10 @@
   MayLoad = 0;
   MayStore = 0;
 
+  if (PatternGenArgs::Args.DumpMIR) {
+    LLVM_DEBUG(MF.dump());
+  }
+
   std::string InstName = MF.getName().str().substr(4);
   std::string InstNameO = InstName;
   ++PatternGenNumInstructionsProcessed;
@@ -1362,10 +1394,6 @@
     return true;
   }
 
-  llvm::outs() << "Pattern for " << InstName << ": " << Node->patternString()
-               << '\n';
-  ++PatternGenNumPatternsGenerated;
-
   LLT OutType = LLT();
   std::string OutsString;
   std::string InsString;
@@ -1409,6 +1437,11 @@
     }
   }
 
+  llvm::outs() << "Pattern for " << InstName << ": " << Node->patternString()
+               << '\n';
+  ++PatternGenNumPatternsGenerated;
+
+
   InsString = InsString.substr(0, InsString.size() - 2);
   OutsString = OutsString.substr(0, OutsString.size() - 2);
 

llvm/tools/pattern-gen/CMakeLists.txt

@@ -20,6 +20,8 @@ set(LLVM_LINK_COMPONENTS
   TransformUtils
   Vectorize
   Passes
+  RISCVCodeGen
+  RISCVDesc
   )
 
 include_directories(../../lib/Target/RISCV)

llvm/tools/pattern-gen/Main.cpp

@@ -1,3 +1,3 @@
 #include <cstdio>
 #include <ctype.h>
 #include <exception>
@@ -55,6 +55,8 @@
                                 cl::cat(ToolOptions));
 static cl::opt<bool> PrintIR("print-ir", cl::desc("Print LLVM-IR module."),
                              cl::cat(ToolOptions));
+static cl::opt<bool> PrintMIR("print-mir", cl::desc("Print LLVM-MIR functions."),
+                             cl::cat(ToolOptions));
 static cl::opt<bool> NoExtend(
     "no-extend",
     cl::desc("Do not apply CDSL typing rules (Use C-like type inference)."),
@@ -128,15 +130,6 @@
     auto Mod = std::make_unique<Module>("mod", Ctx);
     auto Instrs = ParseCoreDSL2(Ts, (XLen == 64), Mod.get(), NoExtend);
 
-    if (irOut) {
-      std::string Str;
-      raw_string_ostream OS(Str);
-      OS << *Mod;
-      OS.flush();
-      irOut << Str << "\n";
-      irOut.close();
-    }
-
     if (!SkipVerify)
       if (verifyModule(*Mod, &errs()))
         return -1;
@@ -165,9 +158,14 @@
     PGArgsStruct Args{.Mattr = "",
                       .OptLevel = Opt,
                       .Predicates = Predicates,
-                      .Is64Bit = (XLen == 64)};
+                      .Is64Bit = (XLen == 64),
+                      .DumpMIR = PrintMIR.getValue()};
 
     optimizeBehavior(Mod.get(), Instrs, irOut, Args);
+
+    if (irOut)
+      irOut.close();
+
     if (PrintIR)
       llvm::outs() << *Mod << "\n";
     if (!SkipFmt)

llvm/tools/pattern-gen/PatternGen.hpp

@@ -1,3 +1,3 @@
 #pragma once
 #include "lib/InstrInfo.hpp"
 #include "llvm/CodeGen/SelectionDAG.h"
@@ -10,6 +10,7 @@
     llvm::CodeGenOptLevel OptLevel;
     std::string Predicates;
     bool Is64Bit;
+    bool DumpMIR;
 };
 
 int optimizeBehavior(llvm::Module* M, std::vector<CDSLInstr> const& Instrs, std::ostream& OstreamIR, PGArgsStruct Args);

llvm/tools/pattern-gen/lib/InstrInfo.hpp

@@ -1,3 +1,3 @@
 #pragma once
 #include "llvm/ADT/SmallVector.h"
 #include <cstdint>
@@ -38,10 +38,12 @@
         std::string_view ident;
         uint32_t identIdx;
         FieldType type;
+        std::string llvm_type;
     };
 
     uint8_t size;
     std::string name;
+    std::string llvm_instr;
     std::string mnemonic;
     std::string argString;