VHDL UART

Description

A VHDL UART for communicating over a serial link with an FPGA. This example implements a loopback so that data received by the FPGA will be returned down the serial link.

The default settings for the link are 115200 BAUD, 8 Data, 1 Stop, No parity.

Further reading

http://www.bytebash.com/2011/10/rs232-uart-vhdl/