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This PR overhauls the instruction parsing and execution logic with the goal of CPU and memory being updated in a cycle accurate fashion.
To do so, each virtual instruction's execution is now broken up into a series of "ticks" which correspond to the machine cycles that are taken during its execution. During each tick, the CPU performs a single read or write from memory and optional ALU and IDU actions. Then, the memory map is ticked.
Note, the goal of this PR is not to ensure that existing (but failing) ROM tests which assert cycle accuracy pass. Rather, this lays the ground work for those tests.