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MichaelBell
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Jan 9, 2025
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| reg [31:0] registers [1:NUM_REGS-1]; | ||
| reg [XLEN-1:0] registers [1:NUM_REGS-1]; |
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There's some 31s further down that will need fixing.
MichaelBell
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cpu/core.v
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This is certainly interesting, but I don't think I would tape out a 64-bit version myself. However, if you're interested in doing that (or using an RV64E TinyQV for another purpose!) I would be happy to accept the change so we can stay on a common code base, providing we can find a fix for the test duplication. |
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I tried changing decode to add 64bit specific opcodes and the way generate works in verilog make that fairly annoying, so I'm not sure what the best approach would be here. I wouldn't want to make the code harder to read/maintain just for the curiosity of trying out RV74. |
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I'd like a better solution to testing than copying the entire thing but I'm not sure how to get cocotb to specify the parameters in the tb, though some searching suggests that there is a way, I didn't find what that way was.