APB RAM Design and UVM Verification

This repository contains a SystemVerilog implementation of an APB-compliant RAM along with a complete UVM-based verification environment.
The project demonstrates both RTL design and protocol-level verification for the AMBA APB bus.

It is intended as a learning and reference project for VLSI students and engineers practicing bus protocols, constrained-random verification, and UVM architecture.

---

📌 Design Overview

• Protocol: AMBA APB
• Memory: 32 locations × 32-bit wide
• Address Range: 0–31 (out-of-range accesses generate slave error)
• Reset: Active-low (presetn)
• Clock: pclk

APB Slave Features

• Supports read and write transactions
• Implements APB protocol phases:
  • IDLE
  • SETUP
  • ACCESS
  • TRANSFER
• Generates PSLVERR for invalid addresses
• Uses PREADY for transaction completion
• Synchronous design with clean state transitions

---

🧠 RTL Architecture

• apb_ram

  • Finite State Machine (FSM) controlling APB phases
  • Internal memory array (mem[32])
  • Address checking and error handling

• apb_if

  • APB interface abstraction for UVM connectivity

---

🧪 Verification Environment (UVM)

The verification environment is fully UVM-compliant and includes:

Components

• Transaction: APB transaction with constrained fields
• Sequences:
  • Write transactions
  • Read transactions
  • Write followed by read
  • Bulk write and bulk read
  • Error injection (invalid address access)
  • Reset testing
• Driver: Drives APB protocol signals
• Monitor: Observes bus activity
• Scoreboard: Verifies read/write correctness
• Agent: Active APB agent
• Environment: Connects agent and scoreboard
• Test: Controls sequence execution

---

🔄 Verification Scenarios Covered

• Valid write and read operations
• Read-after-write data integrity checks
• Bulk memory access
• Invalid address access (slave error detection)
• Reset behavior validation
• Protocol-compliant handshaking

---

▶️ Running the Simulation

Using EDA Playground

1. Open EDA Playground
2. Select SystemVerilog + UVM
3. Paste the RTL and UVM code
4. Run the simulation
5. Observe UVM logs and waveform (dump.vcd)

Local Simulation (Example)

Compatible with:

• Questa / ModelSim
• VCS
• Xcelium

vsim -c tb -do "run -all"