From 2f9870a22467a2d442f9759b4cb6288000d603db Mon Sep 17 00:00:00 2001 From: Steven Malis Date: Thu, 5 Mar 2026 14:22:31 -0500 Subject: [PATCH 1/2] Repo: Fix lints for Rust 1.94 --- .../src/arch/x86_64/address_space.rs | 22 +++++-------------- .../src/platform/hyperv/arch/x86_64/ctx.rs | 3 +-- support/fast_memcpy/benches/perf.rs | 2 +- support/safe_intrinsics/src/lib.rs | 5 +---- vm/devices/net/netvsp/src/lib.rs | 4 ++-- 5 files changed, 11 insertions(+), 25 deletions(-) diff --git a/openhcl/openhcl_boot/src/arch/x86_64/address_space.rs b/openhcl/openhcl_boot/src/arch/x86_64/address_space.rs index 191966ee22..8a444405c5 100644 --- a/openhcl/openhcl_boot/src/arch/x86_64/address_space.rs +++ b/openhcl/openhcl_boot/src/arch/x86_64/address_space.rs @@ -22,7 +22,6 @@ use memory_range::MemoryRange; use x86defs::X64_LARGE_PAGE_SIZE; use x86defs::tdx::TDX_SHARED_GPA_BOUNDARY_ADDRESS_BIT; use zerocopy::FromBytes; -use zerocopy::Immutable; use zerocopy::IntoBytes; use zerocopy::KnownLayout; @@ -38,10 +37,10 @@ const PAGE_TABLE_ENTRY_COUNT: usize = 512; const X64_PAGE_SHIFT: u64 = 12; const X64_PTE_BITS: u64 = 9; -#[derive(Debug, IntoBytes, Immutable, KnownLayout, FromBytes)] +#[derive(Debug, IntoBytes, KnownLayout, FromBytes)] #[repr(transparent)] struct PageTableEntry { - entry: u64, + entry: AtomicU64, } #[derive(Debug, Copy, Clone)] pub enum PageTableEntryType { @@ -49,21 +48,12 @@ pub enum PageTableEntryType { } impl PageTableEntry { - fn atomic_pte<'a>(&self) -> &'a AtomicU64 { - // SAFETY: Casting a u64 to an atomic u64 via pointer is safe. All accesses to the u64 are - // consistently performed using this method. - unsafe { - let ptr = &self.entry as *const u64; - &*ptr.cast() - } - } - fn write_pte(&mut self, val: u64) { - self.atomic_pte().store(val, Ordering::SeqCst); + self.entry.store(val, Ordering::SeqCst); } fn read_pte(&self) -> u64 { - self.atomic_pte().load(Ordering::Relaxed) + self.entry.load(Ordering::Relaxed) } /// Set an AMD64 PDE to either represent a leaf 2MB page or PDE. @@ -91,7 +81,7 @@ impl PageTableEntry { } pub fn is_large_page(&self) -> bool { - self.entry & X64_PTE_LARGE_PAGE == X64_PTE_LARGE_PAGE + self.read_pte() & X64_PTE_LARGE_PAGE == X64_PTE_LARGE_PAGE } pub fn get_addr(&self) -> u64 { @@ -126,7 +116,7 @@ impl PageTableEntry { } #[repr(C)] -#[derive(Debug, IntoBytes, Immutable, KnownLayout, FromBytes)] +#[derive(Debug, IntoBytes, KnownLayout, FromBytes)] struct PageTable { entries: [PageTableEntry; PAGE_TABLE_ENTRY_COUNT], } diff --git a/opentmk/src/platform/hyperv/arch/x86_64/ctx.rs b/opentmk/src/platform/hyperv/arch/x86_64/ctx.rs index ae03cb9d02..5ea62fee91 100644 --- a/opentmk/src/platform/hyperv/arch/x86_64/ctx.rs +++ b/opentmk/src/platform/hyperv/arch/x86_64/ctx.rs @@ -440,8 +440,7 @@ impl VtlPlatformTrait for HvTestCtx { impl HvTestCtx { /// Return the index of the VP that is currently executing this code. pub(crate) fn get_vp_idx() -> u32 { - // SAFETY: we are executing a valid CPUID instruction. - let result = unsafe { core::arch::x86_64::__cpuid(0x1) }; + let result = core::arch::x86_64::__cpuid(0x1); (result.ebx >> 24) & 0xFF } diff --git a/support/fast_memcpy/benches/perf.rs b/support/fast_memcpy/benches/perf.rs index b7f4b3be53..78d3d7ef32 100644 --- a/support/fast_memcpy/benches/perf.rs +++ b/support/fast_memcpy/benches/perf.rs @@ -48,7 +48,7 @@ fn do_bench_memcpy( struct Aligned { _data: [u8; N], } - let count = len.next_multiple_of(N) / N; + let count = len.div_ceil(N); let elt = Aligned { _data: [0; N] }; let src = vec![elt; count]; let mut dest = vec![elt; count]; diff --git a/support/safe_intrinsics/src/lib.rs b/support/safe_intrinsics/src/lib.rs index dc56d98830..b53a8a7057 100644 --- a/support/safe_intrinsics/src/lib.rs +++ b/support/safe_intrinsics/src/lib.rs @@ -13,10 +13,7 @@ /// Invokes the cpuid instruction with input values `eax` and `ecx`. #[cfg(target_arch = "x86_64")] pub fn cpuid(eax: u32, ecx: u32) -> core::arch::x86_64::CpuidResult { - // SAFETY: this instruction is always safe to invoke. If the instruction is - // for some reason not supported, the process will fault in an OS-specific - // way, but this will not cause memory safety violations. - unsafe { core::arch::x86_64::__cpuid_count(eax, ecx) } + core::arch::x86_64::__cpuid_count(eax, ecx) } /// Invokes the rdtsc instruction. diff --git a/vm/devices/net/netvsp/src/lib.rs b/vm/devices/net/netvsp/src/lib.rs index a04b03bfa6..b78f3ab186 100644 --- a/vm/devices/net/netvsp/src/lib.rs +++ b/vm/devices/net/netvsp/src/lib.rs @@ -2224,8 +2224,8 @@ impl NvspMessage { // Note that vmbus packets are always 8-byte multiples, so round the // protocol package size up. let len = match self.size { - PacketSize::V1 => const { protocol::PACKET_SIZE_V1.next_multiple_of(8) / 8 }, - PacketSize::V61 => const { protocol::PACKET_SIZE_V61.next_multiple_of(8) / 8 }, + PacketSize::V1 => const { protocol::PACKET_SIZE_V1.div_ceil(8) }, + PacketSize::V61 => const { protocol::PACKET_SIZE_V61.div_ceil(8) }, }; &self.buf[..len] } From 37a0544924c2cb9485a4b9b2924804ce142eba90 Mon Sep 17 00:00:00 2001 From: Steven Malis Date: Thu, 5 Mar 2026 15:13:27 -0500 Subject: [PATCH 2/2] Undo cpuid safety change --- opentmk/src/platform/hyperv/arch/x86_64/ctx.rs | 3 ++- support/safe_intrinsics/src/lib.rs | 5 ++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/opentmk/src/platform/hyperv/arch/x86_64/ctx.rs b/opentmk/src/platform/hyperv/arch/x86_64/ctx.rs index 5ea62fee91..ae03cb9d02 100644 --- a/opentmk/src/platform/hyperv/arch/x86_64/ctx.rs +++ b/opentmk/src/platform/hyperv/arch/x86_64/ctx.rs @@ -440,7 +440,8 @@ impl VtlPlatformTrait for HvTestCtx { impl HvTestCtx { /// Return the index of the VP that is currently executing this code. pub(crate) fn get_vp_idx() -> u32 { - let result = core::arch::x86_64::__cpuid(0x1); + // SAFETY: we are executing a valid CPUID instruction. + let result = unsafe { core::arch::x86_64::__cpuid(0x1) }; (result.ebx >> 24) & 0xFF } diff --git a/support/safe_intrinsics/src/lib.rs b/support/safe_intrinsics/src/lib.rs index b53a8a7057..dc56d98830 100644 --- a/support/safe_intrinsics/src/lib.rs +++ b/support/safe_intrinsics/src/lib.rs @@ -13,7 +13,10 @@ /// Invokes the cpuid instruction with input values `eax` and `ecx`. #[cfg(target_arch = "x86_64")] pub fn cpuid(eax: u32, ecx: u32) -> core::arch::x86_64::CpuidResult { - core::arch::x86_64::__cpuid_count(eax, ecx) + // SAFETY: this instruction is always safe to invoke. If the instruction is + // for some reason not supported, the process will fault in an OS-specific + // way, but this will not cause memory safety violations. + unsafe { core::arch::x86_64::__cpuid_count(eax, ecx) } } /// Invokes the rdtsc instruction.