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<!DOCTYPE html>
<html lang="ja">
<head>
<meta charset="utf-8" />
<title>NES</title>
<meta name="viewport" content="width=device-width,initial-scale=1" />
<link rel="icon" href="nes.png" type="image/png">
<style>
:root {
color-scheme: light dark;
}
@font-face {
font-family: "Renner";
src: url("./Renner.ttf") format("truetype");
font-display: swap;
}
body {
background:rgb(0, 0, 0);
font-family: "Renner", sans-serif;
margin: 0;
padding:0;
}
h1{
font-weight:300;
font-size:25px;
}
header {
display: flex;
gap: 12px;
align-items: center;
margin-bottom: 12px;
}
canvas{
height: 100%; /* コンテナ幅に合わせる */
aspect-ratio: 256 / 240; /* 内部解像度の比率を維持 */
image-rendering: pixelated;
border: 1px solid #000000;
background: #000;
}
.row {
padding-top:0px;
height:83vh;
justify-content: center;
display: flex;
gap: 12px;
align-items: center;
}
.mono {
font-size:20px;
}
small {
opacity: 0.7;
}
button{
font-family: "Renner", sans-serif;
padding:10px;
background:rgb(0, 0, 0);
color:rgb(255, 255, 255);
border:1px solid rgb(255, 255, 255);
}
.file-input {
display: none; /* 本体は隠す */
}
.file-label {
display: inline-block;
padding: 10px 16px;
background: #000000;
color: white;
border:1px solid white;
border-radius: 0px;
cursor: pointer;
font-size: 14px;
transition: background 0.2s;
}
</style>
</head>
<body>
<header>
<h1>FAMICOMU</h1>
<select id="romSelect">
<option value="">-- サーバーROMを選択 --</option>
<option value="snow.nes">snow.nes</option>
<option value="cmc.nes">cmc.nes</option>
<option value="roms/sw.nes">sw.nes</option>
<option value="roms/bs.nes">bs.nes</option>
<option value="roms/dh2.nes">dh.nes</option>
</select>
<label class="file-label">
Select
<input id="rom" type="file" class="file-input">
</label>
<span id="file-name"></span>
<button id="fullscreenBtn">Fullscreen</button>
<button id="start" disabled>Start</button>
<div class="mono" id="status">No ROM</div>
<div><span class="mono">CPU PC:</span> <span id="pc" class="mono">0x0000</span></div>
</header>
<div class="row">
<canvas id="screen" width="256" height="240"></canvas>
<div style="display:none">
<div><b>FPS:</b> <span id="fps">0</span></div>
<div><b>CPU PC:</b> <span id="pc" class="mono">0x0000</span></div>
<div><b>Cycles:</b> <span id="cyc" class="mono">0</span></div>
<div><b>VRAM V:</b><span id="pcp" class="mono">0x0000</span></div>
<div><b>VRAM T:</b><span id="ppx" class="mono">0x0000</span></div>
<div><b>CPU S:</b><span id="ram" class="mono">0x0000</span></div>
<div><b>CPU P:</b><span id="mapper" class="mono">0x0000</span></div>
<small
>Skeleton: Mapper0, iNES, PPU frame timing + NMI, CPU bus/IRQs, opcode
hooks</small
>
</div>
</div>
<script type="module">
const u8 = (n) => n & 0xff;
const u16 = (n) => n & 0xffff;
const lo = (n) => n & 0xff;
const hi = (n) => (n >> 8) & 0xff;
const NES_PALETTE = [
0x666666ff, 0x002a88ff, 0x1412a7ff, 0x3b00a4ff, 0x5c007eff, 0x6e0040ff,
0x6c0600ff, 0x561d00ff, 0x333500ff, 0x0b4800ff, 0x005200ff, 0x004f08ff,
0x00404dff, 0x000000ff, 0x000000ff, 0x000000ff, 0xadadadff, 0x155fd9ff,
0x4240ffff, 0x7527feff, 0xa01accff, 0xb71e7bff, 0xb53120ff, 0x994e00ff,
0x6b6d00ff, 0x388700ff, 0x0c9300ff, 0x008f32ff, 0x007c8dff, 0x000000ff,
0x000000ff, 0x000000ff, 0xffffffff, 0x64b0ffff, 0x9290ffff, 0xc676ffff,
0xf26affff, 0xff6eccff, 0xff8170ff, 0xea9e22ff, 0xbcbe00ff, 0x88d800ff,
0x5ce430ff, 0x45e082ff, 0x48cddeff, 0x4f4f4fff, 0x000000ff, 0x000000ff,
0xffffffff, 0xc0dfffff, 0xd3d2ffff, 0xe8c8ffff, 0xfbc2ffff, 0xffc4eaff,
0xffccc5ff, 0xf7d8a5ff, 0xe4e594ff, 0xcfef96ff, 0xbdf4abff, 0xb3f3ccff,
0xb5ebf2ff, 0xb8b8b8ff, 0x000000ff, 0x000000ff,
];
class IMapper {
constructor(cart, bus) {
this.cart = cart;
this.bus = bus;
this.prg = cart.prg;
this.chr = cart.chr || new Uint8Array(0x2000);
this.chrIsRAM = cart.chrIsRAM;
this.mirrorMode = cart.mirror;
this.prgRAM = cart.prgRAM || new Uint8Array(0x2000);
}
cpuRead(addr) {
return 0;
}
cpuWrite(addr, val) {}
ppuRead(addr) {
return 0;
}
ppuWrite(addr, val) {}
mirroring() {
return this.mirrorMode;
}
getSaveRAM() {
return this.prgRAM;
}
}
const MapperRegistry = {
0: (cart, bus) => new Mapper0(cart, bus),
1: (cart, bus) => new Mapper1(cart, bus),
2: (cart, bus) => new Mapper2(cart, bus),
3: (cart, bus) => new Mapper3(cart, bus),
4: (cart, bus) => new Mapper4(cart, bus),
5: (cart, bus) => new Mapper5(cart, bus), // MMC5
7: (cart, bus) => new Mapper7(cart, bus),
9: (cart, bus) => new Mapper9(cart, bus),
10: (cart, bus) => new Mapper10(cart, bus),
11: (cart, bus) => new Mapper11(cart, bus),
13: (cart, bus) => new Mapper13(cart, bus),
15: (cart, bus) => new Mapper15(cart, bus),
16: (cart, bus) => new Mapper16(cart, bus),
18: (cart, bus) => new Mapper18(cart, bus),
19: (cart, bus) => new Mapper19(cart, bus), // Namco 163
21: (cart, bus) => new Mapper21(cart, bus), // VRC4a
22: (cart, bus) => new Mapper22(cart, bus), // VRC2a
23: (cart, bus) => new Mapper23(cart, bus), // VRC2b/4e
24: (cart, bus) => new Mapper24(cart, bus), // VRC6a
25: (cart, bus) => new Mapper25(cart, bus), // VRC4b/d
26: (cart, bus) => new Mapper26(cart, bus), // VRC6b
30: (cart, bus) => new Mapper30(cart, bus),
34: (cart, bus) => new Mapper34(cart, bus),
66: (cart, bus) => new Mapper66(cart, bus),
69: (cart, bus) => new Mapper69(cart, bus), // FME-7
71: (cart, bus) => new Mapper71(cart, bus),
73: (cart, bus) => new Mapper73(cart, bus), // VRC3
75: (cart, bus) => new Mapper75(cart, bus),
76: (cart, bus) => new Mapper76(cart, bus),
78: (cart, bus) => new Mapper78(cart, bus),
79: (cart, bus) => new Mapper79(cart, bus),
85: (cart, bus) => new Mapper85(cart, bus), // VRC7
86: (cart, bus) => new Mapper86(cart, bus),
87: (cart, bus) => new Mapper87(cart, bus),
88: (cart, bus) => new Mapper88(cart, bus),
89: (cart, bus) => new Mapper89(cart, bus),
93: (cart, bus) => new Mapper93(cart, bus),
94: (cart, bus) => new Mapper94(cart, bus),
95: (cart, bus) => new Mapper95(cart, bus),
97: (cart, bus) => new Mapper97(cart, bus),
105: (cart, bus) => new Mapper105(cart, bus),
113: (cart, bus) => new Mapper113(cart, bus),
115: (cart, bus) => new Mapper115(cart, bus),
118: (cart, bus) => new Mapper118(cart, bus),
119: (cart, bus) => new Mapper119(cart, bus),
144: (cart, bus) => new Mapper144(cart, bus),
148: (cart, bus) => new Mapper148(cart, bus),
152: (cart, bus) => new Mapper152(cart, bus),
180: (cart, bus) => new Mapper180(cart, bus),
184: (cart, bus) => new Mapper184(cart, bus),
185: (cart, bus) => new Mapper185(cart, bus),
206: (cart, bus) => new Mapper206(cart, bus),
228: (cart, bus) => new Mapper228(cart, bus),
};
function createMapper(cart, bus) {
const ctor = MapperRegistry[cart.mapper];
if (!ctor) throw new Error(`未対応マッパー: ${cart.mapper}`);
return ctor(cart, bus);
}
class Mapper0 extends IMapper {
constructor(cart) {
super(cart);
this.prg = cart.prg;
this.prgSize = this.prg.length;
if (cart.chr && cart.chr.length > 0) {
// CHR ROM
this.chr = cart.chr;
this.chrIsRAM = false;
} else {
// CHR RAM (8KB)
this.chr = new Uint8Array(0x2000);
this.chrIsRAM = true;
}
}
cpuRead(addr) {
if (addr < 0x8000) return 0;
let a = addr - 0x8000;
if (this.prgSize === 0x4000) a &= 0x3FFF;
return this.prg[a];
}
cpuWrite(addr, val) {
// Mapper 0: 何もしない
}
ppuRead(addr) {
if (addr < 0x2000) {
return this.chr[addr & 0x1FFF];
}
return 0;
}
ppuWrite(addr, val) {
if (addr < 0x2000 && this.chrIsRAM) {
this.chr[addr & 0x1FFF] = val & 0xFF;
}
}
}
class Mapper2 extends IMapper {
constructor(cart) {
super(cart);
this.prg = cart.prg;
this.chr = cart.chr || new Uint8Array(0x2000);
this.chrIsRAM = cart.chrIsRAM;
this.bank = 0;
this.fixedBank = this.prg.length / 0x4000 - 1; // last bank at $C000-$FFFF
}
cpuRead(addr) {
if (addr < 0x8000) return 0;
if (addr < 0xc000) {
const base = (this.bank & 0x0f) * 0x4000;
return this.prg[base + (addr - 0x8000)];
} else {
const base = this.fixedBank * 0x4000;
return this.prg[base + (addr - 0xc000)];
}
}
cpuWrite(addr, val) {
if (addr >= 0x8000) this.bank = val & 0x0f;
}
ppuRead(addr) {
if (addr < 0x2000) return this.chr[addr];
return 0;
}
ppuWrite(addr, val) {
if (this.chrIsRAM && addr < 0x2000) this.chr[addr] = val;
}
}
class Mapper3 extends IMapper {
constructor(cart) {
super(cart);
this.prg = cart.prg;
this.chr = cart.chr || new Uint8Array(0x2000);
this.chrIsRAM = cart.chrIsRAM;
this.chrBank = 0;
}
cpuRead(addr) {
if (addr < 0x8000) return 0;
const a = addr - 0x8000;
if (this.prg.length === 0x4000) {
// mirror 16K
return this.prg[a & 0x3fff];
}
return this.prg[a];
}
cpuWrite(addr, val) {
if (addr >= 0x8000) this.chrBank = val & 0x03;
}
ppuRead(addr) {
if (addr < 0x2000) {
const base = (this.chrBank & 0x03) * 0x2000; // 8KB bank (一部CNROMは4KB、ROMに依存)
return this.chr[base + addr];
}
return 0;
}
ppuWrite(addr, val) {
if (this.chrIsRAM && addr < 0x2000) this.chr[addr] = val;
}
}
class Mapper1 extends IMapper {
constructor(cart, bus) {
super(cart, bus);
this.shiftReg = 0x10; // 10000b
this.writeCount = 0;
this.control = 0x0C; // PRG mode = 3
this.chrBank0 = 0;
this.chrBank1 = 0;
this.prgBank = 0;
}
resetShift() {
this.shiftReg = 0x10;
this.writeCount = 0;
}
cpuWrite(addr, val) {
if (addr < 0x8000) return;
if (val & 0x80) {
// reset
this.resetShift();
this.control |= 0x0C;
return;
}
// shift in LSB
this.shiftReg = (this.shiftReg >> 1) | ((val & 1) << 4);
this.writeCount++;
if (this.writeCount === 5) {
const reg = (addr >> 13) & 3;
const data = this.shiftReg & 0x1F;
switch (reg) {
case 0:
this.control = data;
break;
case 1:
this.chrBank0 = data;
break;
case 2:
this.chrBank1 = data;
break;
case 3:
this.prgBank = data & 0x0F;
break;
}
this.resetShift();
}
}
cpuRead(addr) {
if (addr < 0x8000) return 0;
const prgMode = (this.control >> 2) & 3;
const prgBanks = this.prg.length / 0x4000;
let bank = 0;
let offset = addr & 0x3FFF;
if (prgMode <= 1) {
// 32KB
bank = (this.prgBank & 0x0E);
return this.prg[(bank * 0x4000) + (addr - 0x8000)];
}
if (prgMode === 2) {
// $8000 fixed
bank = addr < 0xC000 ? 0 : this.prgBank;
} else {
// $C000 fixed
bank = addr < 0xC000 ? this.prgBank : (prgBanks - 1);
}
return this.prg[(bank * 0x4000) + offset];
}
ppuRead(addr) {
if (addr >= 0x2000) return 0;
const chrMode = (this.control >> 4) & 1;
if (!chrMode) {
// 8KB
const base = (this.chrBank0 & 0x1E) * 0x1000;
return this.chr[base + addr];
}
if (addr < 0x1000) {
const base = this.chrBank0 * 0x1000;
return this.chr[base + addr];
} else {
const base = this.chrBank1 * 0x1000;
return this.chr[base + (addr - 0x1000)];
}
}
ppuWrite(addr, val) {
if (this.chrIsRAM && addr < 0x2000) {
this.chr[addr] = val & 0xFF;
}
}
mirroring() {
switch (this.control & 3) {
case 0: return 2; // single-screen lower
case 1: return 3; // single-screen upper
case 2: return 1; // vertical
case 3: return 0; // horizontal
}
}
}
class Mapper4 {
constructor(cart) {
this.cart = cart;
// PRG/CHR data
this.prg = cart.prg; // Uint8Array (ROM)
this.chr = cart.chr;
this.hasChrRam = !!cart.chrIsRAM;
this.prgRam = cart.prgRAM || new Uint8Array(0x2000); // 8KB
this.prgRamEnabled = true;
// Banking registers
this.bankSelect = 0; // $8000
this.bankRegs = new Uint8Array(8); // $8001 target 0..7
this.prgMode = 0; // $8000 bit6
this.chrMode = 0; // $8000 bit7
// Effective bank maps
this.prgBankMap = new Int32Array(4); // 4 x 8KB banks for $8000,$A000,$C000,$E000
this.chrBankMap = new Int32Array(8); // 8 x 1KB banks 0..7
// Mirroring
this.mirror = cart.mirror; // 0:H, 1:V (default from header); overridden by $A000
// IRQ
this.irqLatch = 0; // $C000
this.irqCounter = 0; // internal counter
this.irqReload = false; // latched when $C001 written; reloads on next A12 rise
this.irqEnabled = false; // $E001 enables, $E000 disables+ack
this.irqPending = false;
// A12 edge detector with low filter (~8 PPU cycles)
this.prevA12 = 0;
this.a12LowCooldown = 0; // counts PPU cycles while A12 low
// Init fixed banks
this.resetBanks();
}
resetBanks() {
// Init PRG banks: last 16KB must be fixed across modes
const prg8kBanks = this.prg.length >>> 13; // / 0x2000
// Safety against small PRG sizes
const last = Math.max(0, prg8kBanks - 1);
const last2 = Math.max(0, prg8kBanks - 2);
// Default bank regs:
this.bankRegs[6] = 0; // switchable
this.bankRegs[7] = 1; // switchable
// CHR regs default to 0..7
for (let i = 0; i < 6; i++) this.bankRegs[i] = i; // 0..5
this.bankRegs[6] = 6;
this.bankRegs[7] = 7;
this.updateChrMap();
// Build maps
this.updatePrgMap();
this.updateChrMap();
}
// ----- CPU space -----
cpuRead(addr) {
if (addr >= 0x6000 && addr < 0x8000) {
if (!this.prgRamEnabled) return 0x00;
return this.prgRam[addr & 0x1fff];
}
if (addr >= 0x8000) {
const slot = (addr - 0x8000) >>> 13; // 0..3
const bank = this.prgBankMap[slot]; // 8KB bank index
const off = addr & 0x1fff;
const base = (bank & this._prgBankMask()) << 13;
return this.prg[base + off] | 0;
}
return 0;
}
cpuWrite(addr, val) {
val &= 0xff;
if (addr >= 0x6000 && addr < 0x8000) {
if (!this.prgRamEnabled) return;
this.prgRam[addr & 0x1fff] = val;
return;
}
if (addr >= 0x8000 && addr <= 0x9fff) {
if ((addr & 1) === 0) {
// $8000 even: bank select
this.bankSelect = val & 0x07; // target 0..7
this.prgMode = (val >>> 6) & 1; // bit6
this.chrMode = (val >>> 7) & 1; // bit7
this.updatePrgMap();
this.updateChrMap();
} else {
// $8001 odd: bank data
const i = this.bankSelect & 7;
this.bankRegs[i] = val;
// R0,R1 are 2KB units; R2-R5 are 1KB; R6,R7 are 8KB
if (i <= 5) this.updateChrMap();
else this.updatePrgMap();
}
return;
}
if (addr >= 0xa000 && addr <= 0xbfff) {
if ((addr & 1) === 0) {
// $A000 even: mirroring control (bit0: 0=vertical,1=horizontal)
this.mirror = val & 1 ? 0 : 1; // convert to your mirroring enum: 0:H,1:V
} else {
// $A001 odd: PRG-RAM protect/enable (simplified)
// Common behavior: bit7 enables RAM; bit6 write-protect; implementations vary.
this.prgRamEnabled = (val & 0x80) !== 0 || true; // permissive default if unsure
}
return;
}
if (addr >= 0xc000 && addr <= 0xdfff) {
if ((addr & 1) === 0) {
// $C000 even: IRQ latch
this.irqLatch = val;
} else {
// $C001 odd: IRQ reload on next A12 rising edge
this.irqReload = true;
}
return;
}
if (addr >= 0xe000 && addr <= 0xffff) {
if ((addr & 1) === 0) {
// $E000 even: IRQ disable + acknowledge
this.irqEnabled = false;
this.irqPending = false;
this.cart.bus?.requestIRQ && this.cart.bus.requestIRQ(false); // optional clear
} else {
// $E001 odd: IRQ enable
this.irqEnabled = true;
}
return;
}
}
// ----- PPU space -----
ppuRead(addr) {
addr &= 0x3fff;
if (addr < 0x2000) {
// MMC3 IRQ counter clocks on PPU A12 rising edges, with A12-low filter.
this._clockA12(addr);
const bank1k = this.chrBankMap[addr >>> 10]; // 1KB bank index
const base = (bank1k & this._chrBankMask()) << 10;
const off = addr & 0x03ff;
return this.chr[base + off] | 0;
}
// >= 0x2000 handled by PPU not mapper
return 0;
}
ppuWrite(addr, val) {
addr &= 0x3fff;
val &= 0xff;
if (addr < 0x2000 && this.hasChrRam) {
this._clockA12(addr);
const bank1k = this.chrBankMap[addr >>> 10];
const base = (bank1k & this._chrBankMask()) << 10;
const off = addr & 0x03ff;
this.chr[base + off] = val;
}
}
_prgBankMask() {
return (this.prg.length >>> 13) - 1;
}
_chrBankMask() {
return (this.chr.length >>> 10) - 1;
}
_prgBanks() {
return this.prg.length >>> 13;
} // 8KB単位数
_chrBanks() {
return this.chr.length >>> 10;
} // 1KB単位数
updatePrgMap() {
const prgBanks = this.prg.length >>> 13;
const last = Math.max(0, prgBanks - 1);
const last2 = Math.max(0, prgBanks - 2);
const b6 = this.bankRegs[6] & this._prgBankMask(); // 8KB
const b7 = this.bankRegs[7] & this._prgBankMask();
if (this.prgMode === 0) {
// $8000=b6, $A000=b7, $C000=last2, $E000=last
this.prgBankMap[0] = b6;
this.prgBankMap[1] = b7;
this.prgBankMap[2] = last2;
this.prgBankMap[3] = last;
} else {
// $8000=last2, $A000=b7, $C000=b6, $E000=last
this.prgBankMap[0] = last2;
this.prgBankMap[1] = b7;
this.prgBankMap[2] = b6;
this.prgBankMap[3] = last;
}
}
updateChrMap() {
// R0,R1 are 2KB units; R2-R5 are 1KB units
// Layout depends on chrMode (bit7 of $8000)
const r = this.bankRegs;
// Expand R0,R1 (2KB) into 1KB indices by clearing LSB per spec
const r0 = r[0] & 0xfe;
const r1 = r[1] & 0xfe;
const r2 = r[2],
r3 = r[3],
r4 = r[4],
r5 = r[5];
if (this.chrMode === 0) {
// $0000: R0(2KB) → banks 0,1
this.chrBankMap[0] = r0 + 0;
this.chrBankMap[1] = r0 + 1;
// $0800: R1(2KB) → banks 2,3
this.chrBankMap[2] = r1 + 0;
this.chrBankMap[3] = r1 + 1;
// $1000..$1FFF: R2..R5 as 1KB
this.chrBankMap[4] = r2;
this.chrBankMap[5] = r3;
this.chrBankMap[6] = r4;
this.chrBankMap[7] = r5;
} else {
// $0000..$0FFF: R2..R5
this.chrBankMap[0] = r2;
this.chrBankMap[1] = r3;
this.chrBankMap[2] = r4;
this.chrBankMap[3] = r5;
// $1000: R0(2KB)
this.chrBankMap[4] = r0 + 0;
this.chrBankMap[5] = r0 + 1;
// $1800: R1(2KB)
this.chrBankMap[6] = r1 + 0;
this.chrBankMap[7] = r1 + 1;
}
// Mask to available CHR banks
const m = this._chrBankMask();
for (let i = 0; i < 8; i++) this.chrBankMap[i] &= m;
}
// ----- IRQ clocking by A12 rising edges -----
_clockA12(addr) {
const a12 = (addr >>> 12) & 1;
// Track A12 low time to filter bursts; decrement cooldown when A12==0
if (a12 === 0) {
if (this.a12LowCooldown < 12) this.a12LowCooldown++;
}
// Rising edge detection with low-time qualification
if (this.prevA12 === 0 && a12 === 1 && this.a12LowCooldown >= 8) {
this._onA12Rising();
this.a12LowCooldown = 0; // reset low counter; need fresh low period before next count
}
this.prevA12 = a12;
}
_onA12Rising() {
// Reload behavior
if (this.irqReload || this.irqCounter === 0) {
this.irqCounter = this.irqLatch;
this.irqReload = false;
} else {
this.irqCounter = (this.irqCounter - 1) & 0xff;
}
if (this.irqCounter === 0 && this.irqEnabled) {
this.irqPending = true;
// Signal IRQ to bus/CPU
if (this.cart.bus && this.cart.bus.requestIRQ) {
this.cart.bus.requestIRQ(true);
}
}
}
// Called by Bus for mirroring queries
mirroring() {
// Your Bus expects 0: H, 1: V
return this.mirror;
}
}
class Mapper7 extends IMapper {
constructor(cart, bus) {
super(cart, bus);
this.prgBanks = this.prg.length / 0x8000; // 32KB units
this.bank = 0;
this.singleScreen = 0; // 0/1 → nametable base
}
cpuRead(addr) {
if (addr < 0x6000) return 0;
if (addr < 0x8000) return this.prgRAM[addr - 0x6000];
const base = (this.bank % this.prgBanks) * 0x8000;
return this.prg[base + (addr - 0x8000)];
}
cpuWrite(addr, val) {
val &= 0xff;
if (addr >= 0x6000 && addr < 0x8000) {
this.prgRAM[addr - 0x6000] = val;
return;
}
if (addr >= 0x8000) {
this.bank = val & 0x0f;
this.singleScreen = (val >> 4) & 1; // bit4: mirroring select
}
}
ppuRead(addr) {
if (addr < 0x2000) return this.chr[addr]; // usually CHR-RAM
return 0;
}
ppuWrite(addr, val) {
if (this.chrIsRAM && addr < 0x2000) this.chr[addr] = val & 0xff;
}
// Bus.ntMirror を拡張したくない場合、ここで single-screen を H/V に近似することも可能
mirroring() {
// single-screen: nametable 0 or 1。Bus側が H/V 前提なら暫定で vertical に固定でも可。
// ここでは Bus 側に single-screen を渡せないため、近似として vertical を返す。
return 1;
}
}
class Mapper66 extends IMapper {
constructor(cart, bus) {
super(cart, bus);
this.prgBanks = this.prg.length / 0x8000;
this.chrBanks = Math.max(1, this.chr.length / 0x2000);
this.prgBank = 0;
this.chrBank = 0;
}
cpuRead(addr) {
if (addr < 0x6000) return 0;
if (addr < 0x8000) return this.prgRAM[addr - 0x6000];
const base = (this.prgBank % this.prgBanks) * 0x8000;
return this.prg[base + (addr - 0x8000)];
}
cpuWrite(addr, val) {
val &= 0xff;
if (addr >= 0x6000 && addr < 0x8000) {
this.prgRAM[addr - 0x6000] = val;
return;
}
if (addr >= 0x8000) {
this.prgBank = (val >> 4) & 0x0f; // upper nibble
this.chrBank = (val & 0x0f) % this.chrBanks; // lower nibble
}
}
ppuRead(addr) {
if (addr < 0x2000) {
const base = (this.chrBank % this.chrBanks) * 0x2000;
return this.chr[base + addr];
}
return 0;
}
ppuWrite(addr, val) {
if (this.chrIsRAM && addr < 0x2000) this.chr[addr] = val & 0xff;
}
}
class Mapper9 extends IMapper {
constructor(cart, bus) {
super(cart, bus);
// 4KB CHR banks for left/right halves
this.chrBankL0 = 0; // $0000-$0FFF latch=0
this.chrBankL1 = 0; // latch=1
this.chrBankR0 = 0; // $1000-$1FFF latch=0
this.chrBankR1 = 0; // latch=1
this.latchL = 0; // 0 or 1
this.latchR = 0; // 0 or 1
this.prgBank = 0; // 16KB @ $8000; $C000 固定末尾
this.prgBanks16 = this.prg.length / 0x4000;
this.chrBanks4k = this.chr.length / 0x1000;
// PPU hook
const origPPURead = bus.ppu.ppuRead.bind(bus.ppu);
bus.ppu.ppuRead = (addr) => {
this.onPPUAddr(addr & 0x3fff);
return origPPURead(addr);
};
}
cpuRead(addr) {
if (addr < 0x6000) return 0;
if (addr < 0x8000) return this.prgRAM[addr - 0x6000];
if (addr < 0xc000) {
const base = (this.prgBank % this.prgBanks16) * 0x4000;
return this.prg[base + (addr - 0x8000)];
}
const base = (this.prgBanks16 - 1) * 0x4000;
return this.prg[base + (addr - 0xc000)];
}
cpuWrite(addr, val) {
val &= 0xff;
if (addr >= 0x6000 && addr < 0x8000) {
this.prgRAM[addr - 0x6000] = val;
return;
}
if (addr >= 0xa000 && addr <= 0xafff) {
this.chrBankL0 = val % this.chrBanks4k;
} else if (addr >= 0xb000 && addr <= 0xbfff) {
this.chrBankL1 = val % this.chrBanks4k;
} else if (addr >= 0xc000 && addr <= 0xcfff) {
this.chrBankR0 = val % this.chrBanks4k;
} else if (addr >= 0xd000 && addr <= 0xdfff) {
this.chrBankR1 = val % this.chrBanks4k;
} else if (addr >= 0xe000 && addr <= 0xefff) {
this.prgBank = val & 0x0f;
} else if (addr >= 0xf000 && addr <= 0xffff) {
// mirroring: 0=vertical, 1=horizontal
this.mirrorMode = val & 1 ? 0 : 1; // NES仕様: bit0=mirroring (ここはROMにより差異あり)
}
}
ppuRead(addr) {
if (addr >= 0x2000) return 0;
const a = addr & 0x0fff;
if (addr < 0x1000) {
const base4k =
(this.latchL ? this.chrBankL1 : this.chrBankL0) * 0x1000;
return this.chr[base4k + a];
} else {
const base4k =
(this.latchR ? this.chrBankR1 : this.chrBankR0) * 0x1000;
return this.chr[base4k + a];
}
}
ppuWrite(addr, val) {
if (this.chrIsRAM && addr < 0x2000) this.chr[addr] = val & 0xff;
}
onPPUAddr(addr) {
// Latch points: reads from $0FD8 → L=0, $0FE8 → L=1; similarly on right side $1FD8/$1FE8 → R latch
if ((addr & 0x1000) === 0) {
// left side ($0000-$0FFF)
if ((addr & 0x0fff) === 0x0fd8) this.latchL = 0;
else if ((addr & 0x0fff) === 0x0fe8) this.latchL = 1;
} else {
// right side ($1000-$1FFF)
if ((addr & 0x0fff) === 0x0fd8) this.latchR = 0;
else if ((addr & 0x0fff) === 0x0fe8) this.latchR = 1;
}
}
mirroring() {
return this.mirrorMode;
}
}
class Mapper10 extends IMapper {
constructor(cart, bus) {
super(cart, bus);
// 4KB banks
this.chrLeft0 = 0; // latch=0
this.chrLeft1 = 0; // latch=1
this.chrRight = 0; // fixed 4KB
this.latchL = 0;
this.prgBank = 0; // 16KB @ $8000; $C000 固定末尾
this.prgBanks16 = this.prg.length / 0x4000;
this.chrBanks4k = this.chr.length / 0x1000;
const origPPURead = bus.ppu.ppuRead.bind(bus.ppu);
bus.ppu.ppuRead = (addr) => {
this.onPPUAddr(addr & 0x3fff);
return origPPURead(addr);
};
}
cpuRead(addr) {
if (addr < 0x6000) return 0;
if (addr < 0x8000) return this.prgRAM[addr - 0x6000];
if (addr < 0xc000) {
const base = (this.prgBank % this.prgBanks16) * 0x4000;
return this.prg[base + (addr - 0x8000)];
}
const base = (this.prgBanks16 - 1) * 0x4000;
return this.prg[base + (addr - 0xc000)];
}
cpuWrite(addr, val) {
val &= 0xff;
if (addr >= 0x6000 && addr < 0x8000) {
this.prgRAM[addr - 0x6000] = val;
return;
}
if (addr >= 0xa000 && addr <= 0xafff) {
this.chrLeft0 = val % this.chrBanks4k;
} else if (addr >= 0xb000 && addr <= 0xbfff) {
this.chrLeft1 = val % this.chrBanks4k;
} else if (addr >= 0xc000 && addr <= 0xcfff) {
this.chrRight = val % this.chrBanks4k;
} else if (addr >= 0xd000 && addr <= 0xdfff) {
this.prgBank = val & 0x0f;
} else if (addr >= 0xe000 && addr <= 0xffff) {
// mirroring
this.mirrorMode = val & 1 ? 1 : 0;
}
}
ppuRead(addr) {
if (addr >= 0x2000) return 0;
const a = addr & 0x0fff;
if (addr < 0x1000) {
const base4k =
(this.latchL ? this.chrLeft1 : this.chrLeft0) * 0x1000;
return this.chr[base4k + a];
} else {
const base4k = this.chrRight * 0x1000;
return this.chr[base4k + a];
}
}
ppuWrite(addr, val) {
if (this.chrIsRAM && addr < 0x2000) this.chr[addr] = val & 0xff;
}
onPPUAddr(addr) {
// MMC4 latch points: $0FD8 sets latch=0, $0FE8 sets latch=1 on left
if ((addr & 0x1000) === 0) {
// left
const low = addr & 0x0fff;
if (low === 0x0fd8) this.latchL = 0;
else if (low === 0x0fe8) this.latchL = 1;
}
}
mirroring() {
return this.mirrorMode;
}
}
class Mapper30 extends IMapper {
constructor(cart, bus) {
super(cart, bus);
this.prgBank = 0; // $8000-$BFFF
this.fixedBank = this.prg.length / 0x4000 - 1; // $C000-$FFFF
// CHR-RAM banking: assume 8KB banks over larger RAM (allocate if needed)